Title :
A new and efficient approach for high-speed and very compact realization of Secure Hash Algorithm
Author :
Shahmoradi, Abbas ; Masoumi, Massoud
Author_Institution :
ECE Dept., Semnan Univ., Semnan, Iran
Abstract :
We are proposing that the recently proposed cell-FPGA-like hybrid CMOS/nanodevice architecture is an optimum platform to realize encryption algorithms. Such circuits will combine a semiconductor-transistor (CMOS) stack and a two-level nanowire crossbar with nanoscale two-terminal nanodevices (programmable diodes) formed at each crosspoint. The basic modules of the Secure Hash Algorithm (SHA-512) have been designed using this architecture. In addition, using a custom set of design automation tools, quasi-optimum gate placing, routing and rerouting are provided for SHA-512 building blocks. It is shown that such a design results in a circuit which is defect tolerant, much faster and strikingly denser than its CMOS counterpart.
Keywords :
CMOS integrated circuits; cryptography; field programmable gate arrays; nanoelectronics; SHA-512; cell-FPGA; encryption algorithms; high-speed compact realization; hybrid CMOS; nanodevice architecture; nanoscale two-terminal nanodevices; programmable diodes; quasi-optimum gate placing; secure hash algorithm; semiconductor-transistor stack; two-level nanowire crossbar; CMOS digital integrated circuits; CMOS technology; Cryptography; Design automation; Fabrication; Fabrics; Field programmable gate arrays; NIST; Nanoscale devices; Routing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5117675
