A 2-D Systolic Array for High-Throughput Computation of 2-D Discrete Fourier Transform

Author

Meher, P.K. ; Patra, J.C. ; Vinod, A.P.

Author_Institution

Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1927

Lastpage

1930

Abstract

A simple 2-dimensional architecture is derived for highly concurrent systolization of the 2-dimensional (2D) discrete Fourier transform (DFT). The concurrency of computation has been enhanced and complexity is minimized by the proposed algorithm where an N-point DFT is computed via four inner-products of real-valued data of length ap (N/2). The proposed structure offers significantly lower latency, twice the throughput, and involves nearly the same area-time complexity of the existing multiplier-based DFT structures

Keywords

discrete Fourier transforms; logic design; systolic arrays; 2D discrete Fourier transform; VLSI; concurrent systolization; digital signal processing; high-throughput computation; multiplier-based DFT structures; systolic array; Computer architecture; Concurrent computing; Delay; Digital signal processing chips; Discrete Fourier transforms; Kernel; Signal processing algorithms; Systolic arrays; Throughput; Very large scale integration; Discrete Fourier transform (DFT); VLSI; digital signal processing (DSP) chip; systolic array;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342237

Filename

4145794