DocumentCode
2250327
Title
A Display Order Oriented Scalable Video Decoder
Author
Huang, Jia-Bin ; Lin, Yu-Kun ; Chang, Tian-Sheuan
Author_Institution
Inst. of Electron., Nat. Chiao-Tung Univ., HsinChu
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
1976
Lastpage
1979
Abstract
As network technologies advance, scalable video coding (SVC) has become increasingly popular due to its universal multimedia access capability and competitive compression performance with the state-of-the-art single-layer video coding. However, it´s decoding delay, memory bandwidth and storage requirement are much larger than those of single-layer video coding due to various scalabilities. In this paper, we propose a novel display order instead of direct bitstream order oriented decoding method for the SVC decoder to solve above implementation problems. The analysis for hardware-oriented algorithm shows that the proposed decoding order can reduce the decoding delay, memory bandwidth and storage requirement significantly while is still applicable to various scalable requirements
Keywords
decoding; video coding; H.264/AVC; display order oriented; hardware oriented algorithm; motion compensated temporal filtering; scalable video coding; scalable video decoder; Automatic voltage control; Bandwidth; Decoding; Delay; Displays; Filtering; Scalability; Spatial resolution; Static VAr compensators; Video coding; H.264/AVC; Motion Compensated Temporal Filtering; Scalable Video Coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342274
Filename
4145805
Link To Document