Title :
Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing
Author :
Jiang, Tao ; Chiang, Patrick Y.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Abstract :
Two critical aspects of sense amplifiers (SA), power consumption and clock-to-data delay, are studied and presented for operation under low-supply voltage and driven by low-swing clock. Trade-offs and simulation results are given for a 4-stack StrongARM and a 3-stack double-tail SA, showing up to 50% power reduction in the SA itself and 25% in the clock generation circuit, with acceptable delay degradation.
Keywords :
amplifiers; delays; 3-stack double-tail SA; 4-stack StrongARM; clock generation circuit; clock-to-data delay; delay characterization; delay degradation; low-supply voltage; low-swing clock; low-voltage clock swing; power consumption; sense amplifier; Circuit simulation; Clocks; Computer science; Degradation; Delay; Energy consumption; Low voltage; Operational amplifiers; Power supplies; Tail;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5117715
