Bi-channel memristor memory: A design methodology based on current feedback

In memristor memory design, it is often concentrated on the feedback control effect and not much on the reliability and accuracy. This study adopt an adaptive write, read and erase method, and realize a more resilient memory operation in the face of low yield in the nano-memory technology domain. After analyzing writing, reading and erasing strategies for our target memory cell, we present simulation results that show the feasibility of these writing, reading and erasing procedures. Finally, the narrow current pulse stimulus is compared to the ramp current stimulus, and the latter one is shown to have a faster writing rate. These simulation results are based on a SPICE model built upon the TiO2 memristive device made in HP laboratory.