DocumentCode
2250456
Title
High-level optimization of built-in self test for analog to digital converters
Author
De Venuto, Daniela ; Reyneri, Leonardo
Author_Institution
Politecnico di Bari
fYear
2006
fDate
16-19 May 2006
Firstpage
101
Lastpage
104
Abstract
This paper presents the analysis and optimization of a cheap polynomial fitting method for built-in analog to digital converters testing. Optimization has been carried on using a high-level mixed-signal cosimulation and codesign tool called CodeSimulink. Measurements have validated the high-level model, which therefore proved to be reliable. The optimization carried on by using the proposed approach, allowed to reach the same accuracy (ap90 dB) achieved by the more expensive FFT-based test strategy. The high-level model has then been automatically converted into a VHDL file, which can then be compiled to either FPGA or built-in as an ASIC into the converter itself
Keywords
analogue-digital conversion; built-in self test; circuit testing; curve fitting; hardware description languages; hardware-software codesign; polynomials; ASIC; CodeSimulink; FFT; FPGA; VHDL file; analog to digital converters; built-in self test; codesign tool; high-level mixed-signal cosimulation; high-level optimization; polynomial fitting method; Analog-digital conversion; Application specific integrated circuits; Automatic testing; Built-in self-test; Field programmable gate arrays; Harmonic distortion; Polynomials; Pulse width modulation; Signal generators; Test equipment; FPGA based test method; HW/SW codesign; High-level synthesis; high-resolution ADC testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 2006. MELECON 2006. IEEE Mediterranean
Conference_Location
Malaga
Print_ISBN
1-4244-0087-2
Type
conf
DOI
10.1109/MELCON.2006.1653046
Filename
1653046
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