Title :
A comparative study of low-noise logic cells for mixed mode integrated circuits
Author :
Albuquerque, E. ; Silva, M.
Author_Institution :
INESC, Lisbon, Portugal
Abstract :
The two basic low-noise logic families are CSL, which is the best known, and the recently proposed CBL. In this paper we present the first experimental evaluation of the CBL family, which provides good agreement with the theoretical predictions. We perform a comparative study of the two families supported by measurements on a test chip. This shows (among other conclusions) that most CBL circuits have significantly lower area and slightly lower delay than CSL circuits, for the same static power consumption; however, for very low power levels (slow performance), CSL circuits may have lower area and delay
Keywords :
CMOS logic circuits; delays; integrated circuit noise; logic design; mixed analogue-digital integrated circuits; 0.8 micron; CBL family; CMOS technology; CSL circuits; chip area; current balanced logic; current steering logic; delay; low-noise logic cells; low-noise logic family; mixed mode ICs; mixed mode integrated circuits; CMOS logic circuits; Circuit testing; Coupling circuits; Current supplies; Delay; Integrated circuit noise; Inverters; Logic circuits; MOS devices; Semiconductor device measurement;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857366
