Title :
Parallel architectures for decision-directed RLS-equalization
Author :
Drewes, Christian ; Hammerschmidt, Joachim S. ; Hutter, Andreas A.
Author_Institution :
Inst. for Integrated Circuits, Tech. Univ. Munchen, Germany
Abstract :
Parallel architectures for decision-directed adaptive recursive least-squares (RLS) equalizers based on a QR-decomposition (QRD) using square-root free Givens-rotations are derived that allow very high throughput for broadband applications. We apply an algorithmic optimization that leads to the use of additional fast adder trees together with a re-timing of the required arithmetic components to maximize throughput. A hybrid RLS/least-mean-squares equalizer is further proposed allowing even higher throughput. The complexity of the resulting equalizer structures is compared for an eight-tap decision-feedback equalizer in terms of an equivalent NAND gate count
Keywords :
adaptive equalisers; circuit complexity; decision feedback equalisers; digital signal processing chips; least mean squares methods; least squares approximations; parallel architectures; DSP architecture; QR-decomposition; adaptive RLS equalizers; algorithmic optimization; arithmetic components retiming; broadband applications; complexity comparison; decision-directed RLS equalization; decision-feedback equalizer; eight-tap DFE; equivalent NAND gate count; fast adder trees; hybrid RLS/LMS equalizer; least-mean-squares; parallel architectures; recursive least-squares equalizers; square-root free Givens-rotations; throughput improvement; Adders; Application specific integrated circuits; Arithmetic; Costs; Decision feedback equalizers; Integrated circuit technology; Parallel architectures; Pipeline processing; Resonance light scattering; Throughput;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857371