DocumentCode :
2250737
Title :
Design and Optimization of Self-Biased Complementary Folded Cascode
Author :
Ceperic, Vladimir ; Butkovic, Zeljko ; Baric, Adrijan
Author_Institution :
Fac. of Electr. Eng. & Comput., Zagreb Univ.
fYear :
2006
fDate :
16-19 May 2006
Firstpage :
145
Lastpage :
148
Abstract :
This paper presents design and optimization procedure of a self-biased complementary folded cascade. A self-biased scheme is chosen as a technique that saves power and circuit area, and is less sensitive to process variations. The gain of basic folded cascode is enhanced using a gain boosting approach based on common source self-biased amplifiers. The circuits are optimized using the global optimization approach with the cost function calculated by circuit simulations. The hybrid approach to optimization is used combining the global search strategy using particle swarm optimization (PSO) and direct pattern search (DPS) method used as local search strategy. A complementary folded cascode operational amplifier is designed in the 0.35 mum CMOS technology with the 3.3 V power supply voltage
Keywords :
CMOS integrated circuits; integrated circuit design; operational amplifiers; particle swarm optimisation; search problems; 0.35 mum; 3.3 V; CMOS technology; complementary folded cascode operational amplifier; direct pattern search; global optimization approach; global search strategy; local search strategy; particle swarm optimization; self-biased amplifiers; self-biased complementary folded cascode; Boosting; CMOS technology; Circuit simulation; Cost function; Design optimization; Operational amplifiers; Optimization methods; Particle swarm optimization; Power amplifiers; Power supplies;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrotechnical Conference, 2006. MELECON 2006. IEEE Mediterranean
Conference_Location :
Malaga
Print_ISBN :
1-4244-0087-2
Type :
conf
DOI :
10.1109/MELCON.2006.1653057
Filename :
1653057
Link To Document :
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