DocumentCode
2250761
Title
Desensitization for power reduction in sequential circuits
Author
Chen, Xiangfeng ; Pan, Peicheng ; Liu, C.L.
Author_Institution
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
fYear
1996
fDate
3-7 Jun, 1996
Firstpage
795
Lastpage
800
Abstract
We describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a portion of the circuit will be deactivated. Consequently, average power consumption in the circuit is reduced at a cost of small increases in area and delay. We present an algorithm for determining the desensitizing signal for each register. A significant amount of power reduction is achieved in a number of benchmark circuits according to our experimental results
Keywords
CMOS logic circuits; circuit layout CAD; logic CAD; sequential circuits; CMOS circuits; benchmark circuits; desensitization; desensitizing signal; power reduction; sequential circuits; CMOS digital integrated circuits; CMOS technology; Clocks; Costs; Energy consumption; Logic circuits; Permission; Registers; Sequential circuits; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference Proceedings 1996, 33rd
Conference_Location
Las Vegas, NV
ISSN
0738-100X
Print_ISBN
0-7803-3294-6
Type
conf
DOI
10.1109/DAC.1996.545680
Filename
545680
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