Title :
Low-power and high-SFDR direct digital frequency synthesizer based on hybrid CORDIC algorithm
Author :
Sung, Tze-Yun ; Ko, Lyu-Ting ; Hsin, Hsi-Chin
Author_Institution :
Dept. of Microelectron. Eng., Chung Hua Univ., Hsinchu, Taiwan
Abstract :
This paper describes the architecture and VLSI (very large scale integration) implementation of a direct digital frequency synthesizer (DDFS) based on a hybrid CORDIC (COordinate Rotation DIgital Computer) algorithm. It is shown that the architecture can be implemented as a multiplier-less, small ROM ( 4 times 16 -bit) and pipelined data path. A SoC (system on chip) has been designed with 0.18 mum 1P6M CMOS, and emulated on Xilinx FPGA (field programmable gate array). The proposed technique uses hybrid CORDIC algorithm of sine and cosine functions to achieve more than 84.4-dBc spurious free dynamic range (SFDR). The performances of novel DDFS based on hybrid CORDIC algorithm compares favorably with digital circuit design, power consumption and SFDR.
Keywords :
CMOS logic circuits; CMOS memory circuits; VLSI; direct digital synthesis; field programmable gate arrays; logic design; read-only storage; signal processing; system-on-chip; 1P6M CMOS; ROM; SoC design; VLSI architecture; Xilinx FPGA; coordinate rotation digital computer; field programmable gate array; high-SFDR direct digital frequency synthesizer; hybrid CORDIC algorithm; size 0.18 mum; spurious free dynamic range; system on chip; very large scale integration; Algorithm design and analysis; Computer architecture; Digital circuits; Dynamic range; Energy consumption; Field programmable gate arrays; Frequency synthesizers; Read only memory; System-on-a-chip; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5117732
