DocumentCode :
2250922
Title :
A FIFO data switch design experiment
Author :
Coates, William S. ; Lexau, Jon K. ; Jones, Ian W. ; Fairbanks, Scott M. ; Sutherland, Ivan E.
Author_Institution :
Sun Microsyst. Labs., Palo Alto, CA, USA
fYear :
1998
fDate :
30 Mar-2 Apr 1998
Firstpage :
4
Lastpage :
17
Abstract :
A core problem in many pipelined circuit designs is data-dependent data flow. We describe a methodology and a set of circuit modules to address this problem in the asynchronous domain. We call our methodology P**3, or “P cubed”. Items flowing through a set of FIFO datapaths can be conditionally steered under the control of data carried by other FIFOs. We have used the P**3 methodology to design and implement a FIFO rest chip that uses a data-dependent switch to delete marked data items conditionally. The circuit uses two on-chip FIFO rings as high-speed data sources. It was fabricated through MOSIS using their 0.6 μ CMOS design rules. The peak data switch throughput was measured to be a minimum of 580 million data items per second at nominal Vdd of 3.3 V
Keywords :
CMOS integrated circuits; asynchronous circuits; logic CAD; 0.6 μ CMOS design rules; FIFO data switch design experiment; MOSIS; circuit modules; data-dependent data flow; data-dependent switch; high-speed data sources; pipelined circuit designs; Circuit synthesis; Circuit testing; Clocks; Design methodology; Laboratories; Pipelines; Semiconductor device measurement; Sun; Switches; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1998. Proceedings. 1998 Fourth International Symposium on
Conference_Location :
San Deigo, CA
Print_ISBN :
0-8186-8392-9
Type :
conf
DOI :
10.1109/ASYNC.1998.666490
Filename :
666490
Link To Document :
بازگشت