A low-power 6.6-Gb/s wireline transceiver for low-cost FPGAs in 28nm CMOS

Author

Savoj, Jafar ; Hsieh, Kuang-Yeu ; Fu-Tai An ; Buckley, Mike ; Im, Jay ; Xuewen Jiang ; Jose, Anphy ; Kireev, Vassili ; Kang Wei Lai ; Pham, Hieu ; Turker, Didem ; Wu, Dalei ; Chang, Kuo-Pin

Author_Institution

Xilinx, Inc., San Jose, CA, USA

fYear

2012

fDate

12-14 Nov. 2012

Firstpage

37

Lastpage

40

Abstract

This paper describes the design of a 0.5-6.6Gb/s fully-adaptive low-power quad transceiver embedded in state-of-the-art low-leakage 28nm CMOS FPGAs. The receiver front-end utilizes a wide input common-mode circuit and a 3-stage CTLE to remove the immediate post-cursor ISI. The CTLE is fully adaptive using sign-sign LMS algorithm and edge-based equalization. The transmitter utilizes a 3-tap FIR. The clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The transceiver achieves BER <; 10^-15 at 6.6Gb/s over an 18dB loss channel. Power consumption is 129mW from 1.2V and 1V supplies.

Keywords

CMOS logic circuits; FIR filters; equalisers; field programmable gate arrays; interference suppression; intersymbol interference; least mean squares methods; low-power electronics; phase locked loops; transceivers; 3-stage CTLE; 3-tap FIR; bit rate 6.6 Gbit/s; clocking network; common-mode circuit; edge-based equalization; fully-adaptive low-power quad transceiver; immediate post-cursor ISI; intersymbol interference; loss 18 dB; low-cost FPGA; low-leakage CMOS FPGA; low-power wireline transceiver; power 129 mW; receiver front-end; sign-sign LMS algorithm; size 28 nm; transmitter; voltage 1 V; voltage 1.2 V; wide-range ring-based PLL;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian

Conference_Location

Kobe

Type

conf

DOI

10.1109/IPEC.2012.6522617

Filename

6522617