A branch selection multi-symbol high throughput CABAC decoder architecture for H.264/AVC

Context-based adaptive binary arithmetic coding (CABAC) is a crucial part in H.264/AVC which provides a great compression gain. However, the throughput of CABAC decoder is limited due to the data dependency of decoding algorithm. This paper presents a branch selection hardware architecture which employs the two-symbol parallel decoder by providing all possible choices and then selecting the true one. The proposed CABAC decoder hardware architecture can decode 1.95~1.98 bins per cycle. It is implemented by UMC 90 nm technology with 82 k gate counts at 222 MHz. The maximum throughput is 410 Mbins/sec which is sufficient for decoding video sequence at Level 5.0.