Novel pipelined DWT architecture for dual-line scan

A new discrete wavelet transform (DWT) architecture is proposed in this paper to realize a memory-efficient 2D DWT unit. The proposed DWT architecture alternately processes two lines to remove the transpose buffer whose size is proportional to the image row size. As a result, the hardware complexity of 2D DWT is significantly reduced. To maintain the same critical path delay as that of the previous pipelined DWT, serially concatenated additions are optimized by changing computation topology and applying arithmetic optimization.