Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection

Author

Chen, Wen-Yi ; Ker, Ming-Dou ; Jou, Yeh-Ning ; Huang, Yeh-Jen ; Lin, Geeng-Lih

Author_Institution

Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2009

fDate

24-27 May 2009

Firstpage

385

Lastpage

388

Abstract

With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I_t2) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit design; power integrated circuits; ESD robustness; body current injection; circuit design; high-voltage CMOS IC; latchup immunity; n-channel lateral DMOS; power-rail ESD protection circuit; secondary breakdown current; CMOS technology; Current measurement; Electrostatic discharge; Integrated circuit modeling; Laboratories; Nanoelectronics; Protection; Robustness; Trigger circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5117766

Filename

5117766