DocumentCode
2251594
Title
An augmented chained fault-tolerant ATM switch
Author
Hui, S.K. ; Seman, K. ; Yunus, J.
Author_Institution
Fac. of Electr. Eng., Universiti Teknologi Malaysia, Johor, Malaysia
fYear
2002
fDate
2002
Firstpage
397
Lastpage
400
Abstract
A new fault-tolerant ATM switch architecture based on multistage interconnection network (MIN) was proposed. Multiple paths between each input-output pair of the network are accomplished by connecting together switching elements within the same stage. Besides that, 2n2×2 switching element were distributed between stage n to n+1 in MIN to increase the paths for each input-output pair. It is self-routing, recursive in structure and the smaller network can easily be cascaded to form a larger network. Compared to the conventional mechanism, it reduces delay and gives better performance in term of stability and throughput.
Keywords
asynchronous transfer mode; delays; multistage interconnection networks; packet switching; stability; telecommunication network routing; ATM switch architecture; MIN; augmented chained fault-tolerant ATM switch; delay; multistage interconnection network; recursive structure; self-routing switch; stability; switching elements; throughput; Asynchronous transfer mode; Delay; Distributed processing; Fault tolerance; Joining processes; Multiprocessor interconnection networks; Packet switching; Stability; Switches; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
High Speed Networks and Multimedia Communications 5th IEEE International Conference on
Print_ISBN
0-7803-7600-5
Type
conf
DOI
10.1109/HSNMC.2002.1032616
Filename
1032616
Link To Document