Title :
Multiplier-free realization for decimators in ΣΔ A/D converters
Author :
Tantaratana, Sawasd ; Ghanekar, Sachin P. ; Li, Jianlin
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
We propose a multiplier-free realization for the decimation process in sigma-delta, analog/digital converters. The decimation is realized by multiplier-free comb filter and multiplier-free FIR filter, with appropriate downsampling. The realization uses periodically time-varying (PTV) coefficients and modulators to reduce the hardware. It has a simple structure and easy to implement in VLSI. The coefficients in the realization belong to either the ternary set (0, ±1) or the quinary set (0, ±1, ±2)
Keywords :
VLSI; analogue-digital conversion; delta modulation; digital filters; filtering and prediction theory; modulators; VLSI; decimators; downsampling; modulators; multiplier-free FIR filter; multiplier-free comb filter; periodically time-varying coefficients; quinary set; sigma-delta analog/digital converters; ternary set; Analog computers; Analog-digital conversion; Band pass filters; Delay estimation; Delta-sigma modulation; Demodulation; Finite impulse response filter; Hardware; Signal resolution; TV; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1993. 1993 Conference Record of The Twenty-Seventh Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-4120-7
DOI :
10.1109/ACSSC.1993.342381
