Efficient VLSI design of a reverse RNS converter for new flexible 4-moduli set (2p+k, 2p+1, 2p−1, 22p+1)

In this paper we propose a flexible 4-moduli set (2^p+k, 2^p+1, 2^p-1, 2^2p+1) which is profitable to construct a high-speed residue number system (RNS). We derive a simple reverse conversion algorithm for the proposed moduli set by using Chinese remainder theorem (CRT). The resulting converter architecture mainly consists of simple adders which are suitable to realize an efficient VLSI implementation. Based on TSMC 0.13 mum CMOS technology, the proposed reverse converter demonstrates its superiority in terms of area, delay and power over the converter design for the 4-moduli set (2ⁿ, 2ⁿ-1, 2ⁿ+1, 2²ⁿ+1) under the various dynamic range (DR) requirements. Finally, the chip area, the clock rate and the power consumption of the proposed 32-bit reverse RNS converter are 1227 times 1227um², 105 MHz and 1.3 mW respectively.