Fixed and variable multi-modulus squarer architectures for triple moduli base of RNS

The performance of RNS relies heavily on efficient implementation of residue arithmetic units. In this paper efficient multi-modulus squarer architectures for the moduli 2ⁿ-1, 2ⁿ and 2ⁿ+1 are presented. Two variants of multi-modulus squarer architectures, i.e., fixed and variable multi-modulus architectures, are proposed. Synthesis results based on TSMC 0.18 mum CMOS standard cell implementation demonstrate the performance trade-off between the various designs. Compared to single-modulus architecture for n = 24, fixed multi-modulus architecture provides an area and power savings of 5% and 10%, respectively with similar delay. On the other hand, for the same n, variable multi-modulus architecture reduces the area and power dissipation by 50% and 18%, respectively at the expense of 15% increase in delay.