Crosstalk reduction using buffer insertion

Author

Dubey, Sanjay ; Jorgenson, Joel

Author_Institution

Sun Microsystems Inc, Sunnyvale, CA, USA

Volume

2

fYear

2002

fDate

19-23 Aug. 2002

Firstpage

639

Abstract

Due to the rapid scaling of the CMOS process, the fringing capacitance and the coupling capacitance will play a major role in the noise analysis of the integrated circuits. Coupling induced signal integrity problems will also become more acute. Crosstalk may cause false triggering, improper logic levels, and increased delay or race conditions. In this work, the authors propose a methodology for buffer insertion to reduce on-chip coupling and to achieve timing constraints and requirements.

Keywords

CMOS integrated circuits; VLSI; buffer circuits; capacitance; crosstalk; electromagnetic compatibility; electromagnetic interference; CMOS process scaling; EMC; EMI; buffer insertion; coupling capacitance; crosstalk reduction; delay conditions; false triggering; fringing capacitance; improper logic levels; integrated circuit noise analysis; on-chip coupling reduction; race conditions; timing constraints; timing requirements; 1f noise; Capacitance; Coupling circuits; Crosstalk; Integrated circuit interconnections; Integrated circuit noise; Routing; Very large scale integration; Voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility, 2002. EMC 2002. IEEE International Symposium on

Conference_Location

Minneapolis, MN, USA

Print_ISBN

0-7803-7264-6

Type

conf

DOI

10.1109/ISEMC.2002.1032666

Filename

1032666