Efficient pipelined tunable heterodyne notch filter implementation in FPGAs

Author

Azam, A. ; Sasidaran, D. ; Nelson, K. ; Ford, G. ; Johnson, L. ; Soderstrand, M.

Author_Institution

Sch. of Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK, USA

Volume

5

fYear

2000

fDate

2000

Firstpage

373

Abstract

Through a combination of multiplexing and pipelining it is possible to implement in FPGAs a high-order tunable IIR notch filter using a new digital heterodyne technique. The notch center frequency can be tuned from DC to the Nyquist frequency and the characteristics of the IIR generated notch filter can be reprogrammed for specific applications. A specific implementation of a notch filter suitable for processing digital audio has a sampling frequency of 48 kHz and a maximum clock frequency of 192 kHz, well within the operating range of modern FPGA´s. The whole system can be easily retargeted for an ASIC process such as that available through MOSIS

Keywords

IIR filters; application specific integrated circuits; audio signal processing; circuit tuning; digital filters; field programmable gate arrays; heterodyne detection; notch filters; pipeline processing; 192 kHz; 48 kHz; ASIC process; FPGAs; IIR notch filter; MOSIS; Nyquist frequency; digital audio; digital heterodyne technique; maximum clock frequency; multiplexing; notch center frequency; pipelined tunable heterodyne notch filter; sampling frequency; Application specific integrated circuits; Character generation; Clocks; DC generators; Digital filters; Field programmable gate arrays; Frequency; IIR filters; Pipeline processing; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857442

Filename

857442