Second order TDTL performance analysis and FPGA implementation

This paper presents the architecture, and the mathematical and simulation models of the second order time delay tanlock loop (TDTL). It discusses the transformation of the loop blocks and their subsequent implementation on an FPGA prototype system. The real time results of the FPGA based TDTL system are in agreement with those obtained from simulation. Compared with the first order, the response of the second order loop converges to zero but with a restricted locking range