A spread spectrum clock generator using phase/frequency boosting with a peak power reduction 14.9dB, RMS jitter 1.40ps and power 4.8mW/GHz for USB 3.0

A 2.5 GHz spread spectrum clock generator (SSCG) is proposed for USB 3.0. The low jitter is achieved by setting the normal loop bandwidth to an optimum value, considering both the VCO noise and the quantization noise of ΔΣ modulator. A large peak power reduction is achieved by maintaining a sharp triangular frequency profile through phase/frequency boosting when the phase error between two inputs of PFD exceeds a limit (2π× 2/9 rad). The peak power reduction and the RMS jitter are measured to be -14.9dB at the RBW of 100 KHz and 1.40ps, respectively. The chip area is 0.34mm × 0.36mm in a 0.13um process.