Hardware architecture of an SVD based MIMO OFDM channel estimator

This paper presents an architecture of an SVD based channel estimator. A number of simplifications of the estimator are presented. These simplifications reduces the complexity of the estimator enough to allow for a hardware implementation. A system is defined, in which the channel estimator is to be used. It is shown that with the proposed pilot symbol pattern and the usage of the channel correlation properties the estimator will reduce the number of multiplications with 66 % compared to a brute force attempt. The hardware architecture of the channel estimator is also described. The estimator will have a throughput of 1/6th of the achievable clock speed and the word lengths are chosen such that there will be only a negligible increase in mean square error compared to the floating point case and still a 5 time improvement compared to the least square estimator.