DocumentCode
2253465
Title
Power-aware code scheduling for clusters of active disks
Author
Son, S.W. ; Chen, G. ; Kandemir, M.
Author_Institution
Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA
fYear
2005
fDate
8-10 Aug. 2005
Firstpage
293
Lastpage
298
Abstract
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called cluster of active disks (CAD), where the storage system contains a network of parallel "active disks". Each individual active disk (which includes an embedded processor, disk(s), caches, memory, and interconnect) can perform some application level processing; but, more importantly, the active disks can collectively perform parallel input/output (I/O) and processing, thereby reducing not just the communication latency but I/O latency and computation time as well. The CAD architecture poses many challenges for the next generation software systems at all levels including programming models, operating and runtime systems, application mapping, compilation, parallelization and performance modeling, and evaluation. In this paper, we focus exclusively on code scheduling support required for clusters of active disks. More specifically, we address the problem of code scheduling with the goal of minimizing the power consumption on the disk system. Our experiments indicate that the proposed scheduling approach is very successful in reducing power and generates better results than three other alternate scheduling schemes tested.
Keywords
disc storage; memory architecture; scheduling; CAD architecture; I/O latency; active disks cluster; application mapping; application-level processing; compilation modeling; embedded processor; operating system; parallel active disk; parallel input/output latency; parallelization modeling; performance modeling; power consumption; power-aware code scheduling; programming model; runtime system; storage system; Application software; Concurrent computing; Delay; Embedded computing; Energy consumption; Parallel programming; Power generation; Power system modeling; Processor scheduling; Software systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on
Print_ISBN
1-59593-137-6
Type
conf
DOI
10.1109/LPE.2005.195530
Filename
1522779
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