Title :
A novel VLSI architecture for Lempel-Ziv based data compression
Author :
Lai, Yeong-Kang ; Chen, Kuo-Chen
Author_Institution :
Dept. of Comput. Sci. & Inf., Nat. Dong-Hua Univ., Taiwan
Abstract :
In this paper, a novel VLSI architecture for Lempel-Ziv-based data compression/decompression is presented. Based on the efficient data flow, the proposed architecture can fully exploit the data-reuse to decrease external memory accesses and reduce the pin count. In addition, parameters of the architecture such as the sliding window size, the dictionary size, and the symbol word-length, can be changed to suit the application. The proposed architecture is a high throughput and cost-effective architecture, and very suitable for wireless communication application
Keywords :
VLSI; data compression; digital signal processing chips; encoding; parallel architectures; performance evaluation; DSP chip; Lempel-Ziv based data compression; VLSI architecture; adjustable dictionary size; adjustable sliding window size; adjustable symbol word-length; cost-effective architecture; data compression/decompression; data decompression; data-reuse; external memory accesses reduction; high throughput architecture; pin count reduction; wireless communication application; CADCAM; Computer aided manufacturing; Computer architecture; Computer science; Data compression; Data engineering; Dictionaries; Reduced instruction set computing; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857523
