DocumentCode
2253797
Title
Synonymous address compaction for energy reduction in data TLB
Author
Ballapuram, Chinnakrishnan S. ; Lee, Hsien-Hsin S. ; Prvulovic, Milos
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2005
fDate
8-10 Aug. 2005
Firstpage
357
Lastpage
362
Abstract
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, most processors employ multi-ported L1 caches and TLBs to enable concurrent memory accesses. In this paper, the authors observed that data TLB lookups within a cycle and across consecutive cycles are often synonymous - they go to the same page. To exploit this finding, two new mechanisms were proposed - intra-cycle compaction and inter-cycle compaction of address translation requests in order to save energy in the data TLB. The results showed that average energy savings of 27% using intra-cycle, 42% using inter-cycle in a conventional d-TLB, and 56% using inter-cycle compaction in semantic-aware d-TLBs can be achieved. When these 2 compaction techniques are combined together and applied to both the i-TLB and semantic-aware d-TLBs, an average energy savings of 76% (up to 87%) is obtained.
Keywords
cache storage; memory architecture; storage allocation; virtual storage; address translation; cache memory; concurrent memory access; data TLB; energy reduction; inter-cycle compaction; intra-cycle compaction; synonymous address compaction; virtual memory; CADCAM; Cache memory; Compaction; Computer aided manufacturing; Data engineering; Educational institutions; Embedded computing; High performance computing; Permission; Power engineering and energy;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on
Print_ISBN
1-59593-137-6
Type
conf
DOI
10.1109/LPE.2005.195547
Filename
1522796
Link To Document