• DocumentCode
    2253833
  • Title

    Finite element based solder joint fatigue life predictions for a same die size-stacked-chip scale-ball grid array package

  • Author

    Zahn, Bret A.

  • Author_Institution
    Worldwide Design & Characterization, ChipPAC Inc., Chandler, AZ, USA
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    274
  • Lastpage
    284
  • Abstract
    Viscoplastic finite-element simulation methodologies were utilized to predict solder joint reliability for a same die size, stacked, chip scale, ball grid array package under accelerated temperature cycling conditions (-40C to +125C, 15 min ramps/15 min dwells). The effects of multiple die attach material configurations were investigated along with the thickness of the mold cap and spacer die. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various materials that encompass the stacked die package. Since plastic strain is a dominant parameter that influences low-cycle fatigue, it was used as a basis for evaluation of solder joint structural integrity. The paper discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool and the corresponding results for the solder joint fatigue life.
  • Keywords
    ball grid arrays; chip scale packaging; digital simulation; electronic engineering computing; fatigue; finite element analysis; integrated circuit packaging; integrated circuit reliability; plastic deformation; soldering; thermal expansion; -40 to 125 C; 15 min; ANSYS finite element simulation software tool; BGA package; CSP; FEM; accelerated temperature cycling; ball grid array package; chip scale package; die size package; finite element modeling; low-cycle fatigue; mold cap thickness; multiple die attach material configurations; plastic strain; solder joint fatigue life prediction; solder joint reliability prediction; solder joint structural integrity evaluation; spacer die thickness; stacked package; thermal expansion mismatch; viscoplastic finite-element simulation methodologies; Acceleration; Capacitive sensors; Chip scale packaging; Electronics packaging; Fatigue; Finite element methods; Plastics; Predictive models; Soldering; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 2002. IEMT 2002. 27th Annual IEEE/SEMI International
  • Print_ISBN
    0-7803-7301-4
  • Type

    conf

  • DOI
    10.1109/IEMT.2002.1032767
  • Filename
    1032767