DVB-T Receiver With a Fully Digital I/Q Separator

This paper describes the design of a digital I/Q separator which is applied to DVB-T receivers. The proposed I/Q separator not only avoids problems caused by analog I/Q separators, e.g., gain error, phase error, DC offset, etc., it also resolves the difficulties of prior digital I/Q separators, e.g., large area, large gate count, and high power consumption by insertion of decimation filters. A prototypical system as well as a chip has been designed using 0.18-mum single-poly six-metal CMOS process with core area of 1.59 mm². The total power consumption is merely 433 muW at a 20.0 MHz system clock.