DocumentCode
2254176
Title
Solving wire bond process challenges for QFN packaging
Author
McDivitt, Eric
Author_Institution
Kulicke & Soffa Ind. Inc., Willow Grove, PA, USA
fYear
2002
fDate
2002
Firstpage
391
Lastpage
397
Abstract
The introduction of quad flat non-leaded frames now provides manufacturers with an ability to significantly reduce the finished size of a surface mounted component. Component manufacturers have begun to convert many designs to quad flat non-leaded (QFN) format due to the significant cost savings provided. By widening the frame strip and increasing site density, manufacturers can process a larger number of units through the production line and improve assembly efficiency. In addition, each unit occupies a smaller finished volume, reducing the amount of material and providing a cost savings per package. This paper discusses the challenges of wire bond for QFN package designs and describes how new wire bond capabilities and process optimization can improve production yields.
Keywords
circuit optimisation; integrated circuit economics; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit yield; lead bonding; surface mount technology; QFN format cost reduction; QFN package designs; assembly efficiency; frame strip widening; material requirements reduction; nonleaded frames; process optimization; production line process throughput; production yields; quad flat nonleaded packaging; site density increase; surface mount component size; unit finished volume; wire bond processes; Assembly; Bonding; Costs; Design optimization; Manufacturing processes; Packaging; Production; Strips; Surface finishing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 2002. IEMT 2002. 27th Annual IEEE/SEMI International
Print_ISBN
0-7803-7301-4
Type
conf
DOI
10.1109/IEMT.2002.1032786
Filename
1032786
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