Title :
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms
Author :
Castrillon, Jeronimo ; Velasquez, Ricardo ; Stulova, Anastasia ; Sheng, Weihua ; Ceng, Jianjiang ; Leupers, Rainer ; Ascheid, Gerd ; Meyr, Heinrich
Author_Institution :
Inst. for Integrated Signal Process. Syst. (ISS), RWTH Aachen Univ., Aachen, Germany
Abstract :
Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compiler-centric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.
Keywords :
data flow graphs; multiprocessing systems; parallel programming; program compilers; system-on-chip; GSM; JPEG; Kahn process networks model; MPEG-2; MPSoC platforms; MPSoC programming; compiler centric analysis; multiple applications mapping; multiple applications scheduling; parallel programming model; performance estimation; simultaneous application mapping; synchronous dataflow graph; trace based KPN composability analysis; Analytical models; Computational modeling; Computer networks; Concurrent computing; Parallel programming; Performance analysis; Processor scheduling; Program processors; Programming environments; Simultaneous localization and mapping;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location :
Dresden
Print_ISBN :
978-1-4244-7054-9
DOI :
10.1109/DATE.2010.5456950