DocumentCode
2254477
Title
Serial-parallel multipliers
Author
Yao, Hawkins H. ; Swartzlander, Earl E., Jr.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
1993
fDate
1-3 Nov 1993
Firstpage
359
Abstract
Digital filters and other signal processing applications often involve a large number of multiplications. For many of these applications, the algorithm is sufficiently parallel that an implementation with many serial-parallel multipliers may be more efficient than implementation that uses a few parallel multipliers. This paper examines the design of several serial-parallel multipliers, compares and contrasts the different characteristics and improvements made on these multipliers. Comparison is also made between serial and parallel multipliers to give a rough estimate of the size versus speed trade off for using serial-parallel multipliers
Keywords
digital arithmetic; multiplying circuits; signal processing; digital filters; multiplications; parallel multipliers; serial multipliers; serial-parallel multipliers; signal processing applications; size; speed; Adders; Arithmetic; Clocks; Delay effects; Digital filters; Digital signal processing; Latches; Pipelines; Signal processing algorithms; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1993. 1993 Conference Record of The Twenty-Seventh Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
0-8186-4120-7
Type
conf
DOI
10.1109/ACSSC.1993.342534
Filename
342534
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