Generalized power efficient technique for polyphase comb filter in multi-rate digital receivers

A generalized power efficient clock distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed for any integer decimation factor. The Spartan3 low power FPGAs family is used to implement both proposed and conventional comb filters. From the implementation results it is shown that, applying the proposed technique reduces the dynamic power consumption of second and third order polyphase comb filters up to 56.28% and 50.91%, respectively, depending on the decimation factor and the number of quantizer bits. For particular power consumption, the SNR of a second order ΣΔ modulator is increased, using second and third order modified filters, by 19.4 dB and 16.5 dB respectively, depending on the decimation factor and the number of quantizer bits.