DocumentCode
2254544
Title
A 192MHz to1.946GHz Programmable DLL-Based Frequency Multiplier for RF Applications
Author
Weng, Ro-Min ; Liu, Chun-Yu ; Ming-Hui Liang ; Kuo, Yue-Fang
fYear
2007
fDate
10-14 Jan. 2007
Firstpage
1
Lastpage
2
Abstract
A delay-locked loop based frequency multiplier is presented using tsmc 0.18 mum CMOS process parameters. The multiplication factor N can be chosen as an integral number whereas the output frequency range is from 192 MHz to 1.946 GHz. The total power consumption is less than 5.8 mW with a 1.8 V supply. The locking time of the DLL core is 0.66 mus at 250 MHz. The cycle-to-cycle jitter of the DLL core is 46 ps.
Keywords
CMOS integrated circuits; UHF integrated circuits; VHF circuits; delay lock loops; frequency multipliers; jitter; programmable circuits; 192 MHz to 1.946 GHz; CMOS process parameters; RF applications; cycle-to-cycle jitter; delay-locked loop; power consumption; programmable DLL-based frequency multiplier; Automatic control; Clocks; Delay effects; Filters; Frequency synthesizers; Jitter; Phase frequency detector; Phase locked loops; Radio frequency; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2007. ICCE 2007. Digest of Technical Papers. International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
1-4244-0763-X
Electronic_ISBN
1-4244-0763-X
Type
conf
DOI
10.1109/ICCE.2007.341400
Filename
4146020
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