DocumentCode
2254630
Title
Design and Implementation of a High-Speed Descrambling Engine for Multi-stream CableCARD
Author
Jung, Joon-Young ; Kwon, O-Hyung ; Lee, Soo-In
Author_Institution
Electron. & Telecommun. Res. Inst., Daejeon
fYear
2007
fDate
10-14 Jan. 2007
Firstpage
1
Lastpage
2
Abstract
In this paper, we have present a hardware design of the high-speed descrambling engine for supporting multi channels in multi-stream cableCARD. The designed descrambling engine has been implemented on a FPGA. The presented design has a parallel processing structure that is extendable according to required input bandwidth. Especially we have verified that designed descrambling engine supported up to 200 Mbps input bandwidth.
Keywords
field programmable gate arrays; media streaming; receivers; FPGA; cable receiver; high-speed descrambling engine; multistream cableCARD; parallel processing structure; Bandwidth; Cable TV; Clocks; Communication cables; Decoding; Digital video broadcasting; Engines; Field programmable gate arrays; Hardware; Tuners;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2007. ICCE 2007. Digest of Technical Papers. International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
1-4244-0763-X
Electronic_ISBN
1-4244-0763-X
Type
conf
DOI
10.1109/ICCE.2007.341404
Filename
4146024
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