Title :
Nanometer flip-flops design in the E-D space
Author :
Alioto, Massimo ; Consoli, Elio ; Palumbo, Gaetano
Author_Institution :
Dept. of Inf. Eng., Univ. of Siena, Siena, Italy
Abstract :
A comprehensive design flow, easy to automate with commercial CAD tools, is presented to optimize nanometer FFs under constraints within the E-D space. By referring to practical design cases, transistor sizing is addressed rigorously. Cases of study for FFs in a 65-nm technology are reported for validation.
Keywords :
flip-flops; logic CAD; nanoelectronics; transistors; CAD tools; energy-delay space; nanometer flip-flops design; size 65 nm; transistor sizing; E-D; Energy-Efficiency; Flip-Flops; Nanometer;
Conference_Titel :
Microelectronics (ICM), 2010 International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-61284-149-6
DOI :
10.1109/ICM.2010.5696091
