Digital correction of circuit imperfections in cascaded Σ-Δ modulators composed of 1st-order sections

Author

Davis, Alan J. ; Fischer, Godi ; Hans-Helge, A. ; Hess, Jurgen

Author_Institution

Rhode Island Univ., Kingston, RI, USA

Volume

5

fYear

2000

fDate

2000

Firstpage

689

Abstract

An approach to remove the effects of amplifier finite gain and C-ratio mismatches in the 1-1-1 (MASH) and the 1-1-1-1 cascaded sigma-delta modulator is presented. By correcting the digital outputs with estimates of the parasitic errors due to analog circuit imperfections, uncancelled quantization noise terms can be removed. A 1-1-1-1 cascaded modulator, implemented as a fully differential switched-capacitor circuit, has been fabricated in a 1.2 μm, double-poly, n-well CMOS process. Measurements of the modulator verify that for an amplifier gain of 60 dB, C-ratio mismatch errors of 0.52% and 0.054%, the error correction offers an overall improvement in SNDR of 12-22 dB. A 12 μV_rms sine wave can be restored with a positive SNDR

Keywords

CMOS integrated circuits; cascade networks; quantisation (signal); sigma-delta modulation; switched capacitor networks; 1.2 micron; 60 dB; C-ratio mismatches; MASH; amplifier finite gain; amplifier gain; cascaded sigma-delta modulators; circuit imperfections; double-poly n-well CMOS process; error correction; first-order sections; fully differential switched-capacitor circuit; parasitic errors; uncancelled quantization noise terms; Analog circuits; Circuit noise; Delta modulation; Delta-sigma modulation; Digital modulation; Equations; Error correction; Noise cancellation; Quantization; Switched capacitor circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857577

Filename

857577