A 2048 complex point FFT architecture for digital audio broadcasting system

Author

Choi, Jun-Rim ; Park, Soo-bok ; Han, Dong-Seok ; Park, Se-Ho

Author_Institution

Sch. of Electr. Eng., Kyungpook Nat. Univ., Taegu, South Korea

Volume

5

fYear

2000

fDate

2000

Firstpage

693

Abstract

In this paper, we propose an implementation method for a single-chip 2048 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 2 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding

Keywords

VLSI; cascade networks; digital audio broadcasting; digital signal processing chips; fast Fourier transforms; floating point arithmetic; DRAM-like pipelined commutator architecture; S/N ratio; cascaded blocks; complex point FFT architecture; convergent block floating point algorithm; digital audio broadcasting system; internal bit rounding; required chip area; sequential processing; Decoding; Demodulation; Digital audio broadcasting; Digital modulation; Digital systems; Discrete Fourier transforms; OFDM; Radio broadcasting; Receivers; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857580

Filename

857580