Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programming

We propose an efficient hardware accelerator for the calculation of accumulated values of two-dimensional continuous dynamic programming (2DCDP). The 2DCDP is a powerful optimal pixel-matching algorithm between input and reference images which can be applied to image processing, such as image recognition, image search, feature tracking, 3D reconstruction, and so on. However, it requires large computation time due to its time and space complexities of O(N⁴). We analyze the computation flow of the 2DCDP algorithm and propose a high-performance architecture for a hardware accelerator. Parallelized accumulated minimum local distance calculators and a toggle memory structure are newly introduced to reduce the computation cost and memory. The proposed architecture is implemented into an FPGA, Stratix IV, EP4SE820. Its maximum operation frequency is 125.71 MHz. The preliminary evaluation reveals that the parallel processing by 32 PEs for the accumulated value calculation for 32x32 input and reference images can be sped up to 77 times at the maximum operation frequency of 100 MHz compared to the processing with a multi-core processor.