Title :
Thermal, power, and performance shaping of multicore floorplans
Author_Institution :
Fac. of Inf. Technol., UAE Univ., Al Ain, United Arab Emirates
Abstract :
In this paper, we explore and evaluate multicore processor architecture and floorplans in light of performance, power, and thermal issues. Cores-out-caches-inside and both interleaved and non-interleaved versions of cores-sandwiched-between-caches approaches are considered, with 3 levels of cache memories and ring and bus-based interconnects.
Keywords :
cache storage; circuit layout; low-power electronics; multiprocessing systems; multiprocessor interconnection networks; power aware computing; bus based interconnect; cache memory; cores-out-caches approach; cores-sandwiched-between-caches approach; multicore floorplan; multicore processor architecture; ring based interconnect; Couplings; Delay; Heating; Multicore processing; System-on-a-chip; Wire; Multi-core processors; floorplans; performance; power consumption; thermal management;
Conference_Titel :
Microelectronics (ICM), 2010 International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-61284-149-6
DOI :
10.1109/ICM.2010.5696102
