VLSI design of Reed-Solomon decoder architectures

Author

Lee, Hanho ; Yu, Meng-Lin ; Song, L. Eilea

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

Volume

5

fYear

2000

fDate

2000

Firstpage

705

Abstract

This paper presents VLSI implementations of an 8-error correcting (255, 239) Reed-Solomon (RS) decoder architecture for the optical fibre systems. We present the RS decoders using Euclidean and modified Euclidean algorithms which are regular and simple, and naturally suitable for VLSI implementation. We investigate hardware complexity, clock frequency and data processing rate for those RS decoders. The RS decoder based on the modified Euclidean algorithm operates at a clock frequency of 75 MHz and has a data processing rate of 600 Mbits/s in 0.25-μm CMOS technology with a supply voltage of 2.5 V

Keywords

CMOS digital integrated circuits; Reed-Solomon codes; VLSI; decoding; digital signal processing chips; error correction codes; integrated circuit design; optical fibre communication; 0.25 micron; 2.5 V; 600 Mbit/s; 75 MHz; CMOS technology; Euclidean algorithm; Reed-Solomon decoder architecture; VLSI design; clock frequency; data processing rate; error correction; hardware complexity; modified Euclidean algorithm; optical fibre communication; CMOS process; CMOS technology; Clocks; Data processing; Decoding; Frequency; Hardware; Optical fibers; Reed-Solomon codes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857589

Filename

857589