DocumentCode :
2254943
Title :
An energy-efficient dual sampling SAR ADC with reduced capacitive DAC
Author :
Kim, Binhee ; Yan, Long ; Yoo, Jerald ; Cho, Namjun ; Yoo, Hoi-Jun
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
fYear :
2009
fDate :
24-27 May 2009
Firstpage :
972
Lastpage :
975
Abstract :
This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling step with dual sampling of the analog signal. By sampling and holding the analog signal asymmetrically at both input sides of comparator, the MSB cycling step can be hidden by hold mode. Benefits from this technique, not only the total capacitance of DAC is reduced by half, but also the average switching energy is reduced by 68% compared with conventional SAR ADC. Moreover, switching energy distribution is more uniform over entire output code compared with previous works.
Keywords :
analogue-digital conversion; digital-analogue conversion; sample and hold circuits; MSB cycling step; energy-efficient dual sampling SAR ADC; reduced capacitive DAC; sampling and holding; successive approximation register; switching energy distribution; Capacitance; Capacitors; Delta-sigma modulation; Energy consumption; Energy efficiency; Energy resolution; Sampling methods; Switches; Voltage; Wireless sensor networks;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
Type :
conf
DOI :
10.1109/ISCAS.2009.5117920
Filename :
5117920
Link To Document :
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