Two-phase correlated level shifting switched-capacitor techniques

In this paper, two techniques aiming to improve the performance of the switched-capacitor correlated-level-shifting technique are introduced. While boosting the equivalent opamp dc gain, this technique uses three clock phases. First, a time-shifted two-phase sampling approach is introduced with the addition of another set of sampling capacitors. However, this configuration has the disadvantages of error accumulation, increased mismatch and capacitor memory effects. In the second approach, all of these inconveniences are eliminated using a time-aligned two-phase sampling method. Simulation results show the equivalence of a conventional multiply-by-two switched-capacitor stage using a 60-dB dc gain opamp when compared with the correlated-level-shifting, the time-shifted and the time-aligned configurations, all using opamps with only 30-dB dc gain.