A performance comparison on asynchronous matched-delay templates

The motivation for asynchronous logic at this juncture of CMOS technology is the issues of power density, process variation and integration limit, where synchronous logic is facing a myriad of problems. Asynchronous templates are the fundamental building blocks of asynchronous circuits and systems, and together with asynchronous EDA tools enable the design of complex systems at a high level of abstraction (similar to the RTL-to-GDSII flow in synchronous design). However, akin to the impact of library cells to the overall system performance in the conventional synchronous flow, the diverse availability of asynchronous template libraries requires prudent contemplation. Therefore in this paper, the most eminent matched-delay asynchronous template families reported to date will be presented, and followed by an in-depth comparison of various design figure of merits (FOMs) - template area, static/dynamic capacity, cycle time, latency, throughput and Et². The most aggressive template (GasP) can reach a maximum throughput of 5 Giga items/s on 0.13 mum @ 1.2 V.