• DocumentCode
    2255152
  • Title

    Formal semantics for PSL modeling layer and application to the verification of transactional models

  • Author

    Ferro, Luca ; Pierre, Laurence

  • Author_Institution
    TIMA (CNRS-GrenobleINP-UJF), Grenoble, France
  • fYear
    2010
  • fDate
    8-12 March 2010
  • Firstpage
    1207
  • Lastpage
    1212
  • Abstract
    The IEEE standard PSL is now a commonly accepted specification language for the Assertion-Based Verification (ABV) of complex systems. In addition to its Boolean and Temporal layers, it is syntactically extended with the Modeling layer that borrows the syntax of the HDL is which the PSL assertions are included, to manage auxiliary variables. In this paper we propose a formal, operational, semantics of PSL enriched with the Modeling layer. Moreover we describe the implementation of this notion in our tool for the dynamic ABV of SystemC TLM models. Illustrative examples are presented.
  • Keywords
    formal verification; specification languages; Boolean layers; IEEE standard PSL; PSL modeling layer; SystemC TLM models; assertion-based verification; formal semantics; property specification language; specification language; temporal layers; transactional model verification; Circuit simulation; Debugging; Hardware design languages; Intersymbol interference; Libraries; Productivity; Prototypes; Registers; Specification languages; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4244-7054-9
  • Type

    conf

  • DOI
    10.1109/DATE.2010.5456991
  • Filename
    5456991