DocumentCode :
2255320
Title :
Advanced yield enhancement: computer-based spatial pattern analysis. Part 1
Author :
Lee, Fourmun ; Chatterjee, Arun ; Croley, David
Author_Institution :
Motorola Inc., Chandler, AZ, USA
fYear :
1996
fDate :
12-14 Nov 1996
Firstpage :
409
Lastpage :
415
Abstract :
Wafer-level defect distributions and yield patterns are a significant source of information about the performance of a manufacturing line. Computer-based techniques are ideal for pattern analysis because they provide the ability to quickly perform systematic, repetitive analyses on large data sets. The development of algorithms for computer-based spatial pattern analysis are described and initial test results are presented. Integration of automated spatial pattern analysis into the manufacturing process is discussed
Keywords :
electronic engineering computing; inspection; integrated circuit yield; pattern recognition; production engineering computing; IC manufacturing; algorithm; computer-based spatial pattern analysis; wafer-level defect distribution; yield enhancement; Circuit testing; Computer architecture; Data analysis; Data mining; Inspection; Laboratories; Manufacturing processes; Pattern analysis; Pattern matching; Performance analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996
Conference_Location :
Cambridge, MA
ISSN :
1078-8743
Print_ISBN :
0-7803-3371-3
Type :
conf
DOI :
10.1109/ASMC.1996.558099
Filename :
558099
Link To Document :
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