A generic programmable arbiter with default master grant

Author

Petrot, Frederic ; Hommais, Denis

Author_Institution

Dept. ASIM du LIP6, Univ. Pierre et Marie Curie, Paris, France

Volume

5

fYear

2000

fDate

2000

Firstpage

749

Abstract

This paper details the design and implementation of a centralized bus arbiter implementing programmable fixed priorities arbitration. The arbiter also handles default master grant to the master with highest priority. The arbitration algorithm is computed using a tree of specialized comparators to fully exploit hardware parallelism. The design is implemented as a generic VHDL model whose parameter is the number of masters. After synthesis and place & route, a 16 masters arbiter has a critical path delay of 7.5 ns in 0.5 μm technology

Keywords

CMOS logic circuits; asynchronous circuits; circuit CAD; high-speed integrated circuits; integrated circuit design; logic CAD; programmable circuits; 0.5 micron; 110 MHz; 7.5 ns; arbitration algorithm; centralized bus arbiter; comparator tree; default master grant; generic VHDL model; generic programmable arbiter; hardware parallelism; programmable fixed priorities arbitration; Clocks; Concurrent computing; Delay; Hardware; Master-slave; Parallel processing; Protocols; Real time systems; Tail; Upper bound;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857610

Filename

857610