• DocumentCode
    2255970
  • Title

    Issues on the size and outline of killer defects and their influence on yield modeling

  • Author

    Hess, Christopher ; Weiland, Larg H.

  • Author_Institution
    Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
  • fYear
    1996
  • fDate
    12-14 Nov 1996
  • Firstpage
    423
  • Lastpage
    428
  • Abstract
    Yield prediction models and critical area calculations based on on defects modeled as circular disks. But, the observation of real defects provides mostly irregular defect outlines. For this reason, we investigate the influence of real defect outlines on determining defect size distributions for yield prediction. To collect data on defects, checkerboard test structures were manufactured that enable a precise localization of defects inside large chip areas. Furthermore, we introduce a methodology to calculate a general defect size distribution that includes variety of real defect outlines. So, this realistic size distribution will be compared to defect size distributions based on known yield models to describe defect outlines
  • Keywords
    inspection; integrated circuit testing; integrated circuit yield; statistical analysis; checkerboard test structures; critical area calculations; defect size distributions; electrically measurable faults; irregular defect outlines; killer defects; real defect outlines; yield modeling; yield prediction models; Area measurement; Electric variables measurement; Fault detection; Manufacturing; Optical sensors; Particle measurements; Predictive models; Semiconductor device measurement; Size measurement; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996
  • Conference_Location
    Cambridge, MA
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-3371-3
  • Type

    conf

  • DOI
    10.1109/ASMC.1996.558102
  • Filename
    558102