Title :
Schottky barrier MOSFETs for silicon nanoelectronics
Author_Institution :
Dept. of Electr. & Comput. Eng., Beckman Inst., Urbana, IL, USA
Abstract :
Metal silicide source/drain MOSFETs may provide a simple route to terabit integrated circuits with ~25 nm gate length and ~100 nm overall device size. Potential advantages of this approach are outlined here along with recent progress
Keywords :
MOS integrated circuits; MOSFET; Schottky barriers; elemental semiconductors; nanotechnology; silicon; 100 nm; 25 nm; Schottky barrier MOSFETs; Si; device size; gate length; metal silicide source/drain devices; nanoelectronics; terabit integrated circuits; Carrier confinement; Doping; Electrodes; MOSFETs; Nanoelectronics; P-n junctions; Schottky barriers; Silicides; Silicon; Tunneling;
Conference_Titel :
Frontiers in Electronics, 1997. WOFE '97. Proceedings., 1997 Advanced Workshop on
Conference_Location :
Puerto de la Cruz
Print_ISBN :
0-7803-4059-0
DOI :
10.1109/WOFE.1997.621159
